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TS4974
1W differential audio power amplifier with up/down digital volume control pins
Features

Operates from VCC= 2.5 V to 5.5 V Zero pop & click 1 W output power @ VCC = 5 V, THD = 1%, F = 1 kHz, with 8 load Ultra-low consumption in standby mode (2 A max.) 85 dB PSRR @ 217Hz 16-step digital volume control Two discrete up and down volume control pins Gain range from -33 dB to + 12 dB Integrated debouncing system Ultra-fast start-up time: 15 ms typ. DFN10 3x3 mm (pitch 0.5)
STANDBY GND VINVIN+ BYPASS
DFN10 (3x3)
Pin connections (top view)
1 2 3 4 5 10 9 8 7 6
VCC VOUTVOUT+ UP / DVC DOWN / DVC
Applications

Mobile phones (cellular / cordless) PDAs Laptop/notebook computers Portable audio devices
Description
At 3.3 V, the TS4974 is a dual power audio amplifier capable of delivering 380 mW of continuous RMS output power into a 8 bridgedtied loads with 1% THD+N. An external standby mode control reduces the supply current to less than 2 A. An internal over-temperature shutdown protection is provided. The TS4974 has been designed for high quality audio applications such as mobile phones and minimizes the number of external components necessary.
The TS4974 features 16-step digital volume control through two discrete Up and Down control pins. The start-up gain is internally fixed to -12 dB. An integrated debounce system prevents voltage spikes on the UP/DOWN pins during volume control mode from being taken into account during a debounce time of 10 ms (typ).
May 2007
Rev 4
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www.st.com 25
Contents
TS4974
Contents
1 2 3 4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Typical application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Differential configuration principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Low frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power dissipation and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Assumptions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Decoupling of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Wake-up time (tWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Shutdown time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pop performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Volume setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Notes on PSRR measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 6 7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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TS4974
Absolute maximum ratings
1
Absolute maximum ratings
Table 1.
Symbol VCC Vi Toper Tstg Tj Rthja Pd ESD ESD Latch-up Supply voltage (1) Input voltage
(2)
Absolute maximum ratings
Parameter Value 6 GND to VCC -40 to + 85 -65 to +150 150
(3)
Unit V V C C C C/W
Operating free air temperature range Storage temperature Maximum junction temperature Thermal resistance junction to ambient Power dissipation Human body model Machine model Latch-up immunity Lead temperature (soldering, 10sec)
200 Internally limited(4)
2 200 200 260
kV V mA C
1. All voltage values are measured with respect to the ground pin. 2. The magnitude of input signal must never exceed VCC + 0.3 V / GND - 0.3 V. 3. Device is protected in case of over temperature by a thermal shutdown active @ 150 C. 4. Exceeding the power derating curves during a long period, may provoke abnormal operation.
Table 2.
Symbol VCC VSTBY
Operating conditions
Parameter Supply voltage Standby voltage input: Device ON Device OFF Volume control UP/DOWN voltage input: UP/DOWN mode ON UP/DOWN mode OFF Load resistor Thermal shutdown temperature Thermal resistance junction to ambient (1)
mm2.
Value 2.5 to 5.5 1.5 VSTBY VCC GND VSTBY 0.4 0 VU/D 0.3xVCC, 0.7xVCC VU/D VCC 8 150 80
Unit V V
VU/D RL TSD Rthja
V C C/W
1. With heat sink surface = 125
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Typical application schematics
TS4974
2
Typical application schematics
Figure 1. Typical application schematics for the TS4974
VCC
Rpu1 Volume DOWN S1 470k
VCC
Rpu2 470k
VCC
Volume UP
S2 Cs Rpd1 470k Rpd1 470k 1F
U1
UP
Vin-
P1 Cin1
DIGITAL VOLUME CONTROL
DOWN
Vcc
10
7
6
1
330nF Cin2
Vin-
Vout-
9
Speaker
2
330nF Vin+
Vin+
+
BIAS STBY
STBY GND
Vout+
8
8 Ohms
3
P2 Cb 1F
BYP ASS
TS4974 DFN10
4
STBY control
Table 3.
External component descriptions
Functional description Pair of pull-up (Rpu1, Rpu2) or pull down (Rpd1, Rpd2) resistors that are connected to the digital volume control pins UP/DVC and DOWN/DVC. See Section 4.9: Volume setting on page 20. Input coupling capacitors that block the DC voltage at the amplifier input terminal. They form together with the amplifier's differential input impedance ZIN a first order high pass filter with a -3dB cut-off frequency (fcut-off = 1 / (2 x x ZIN x CIN)). See Section 4.2: Low frequency response on page 16. Supply bypass capacitor that provides power supply filtering. See Section 4.4: Decoupling of the circuit on page 19. Bypass pin capacitor that provides half supply filtering. See Section 4.4: Decoupling of the circuit on page 19.
Components Rpu1, Rpu2 Rpd1, Rpd2
CIN
CS CB
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5
TS4974
Electrical characteristics
3
Table 4.
Symbol ICC ISTBY IU/D Voo Po
Electrical characteristics
VCC = +5 V, GND = 0 V, Tamb = 25 C (unless otherwise specified)
Parameter Supply current, no input signal, no load Standby current No input signal, VSTBY = GND, RL = 8 Volume control UP/DOWN current 0 VU/D 0.3 VCC Output offset voltage No input signal, RL = 8 , G=0 dB, floating inputs Output power THD = 1% max, f = 1 kHz, RL = 8 0.8 Min. Typ. 3.2 300 10 5 1 20 Max. 3.85 2000 Unit mA nA A mV W
Total harmonic distortion + noise THD + N Po = 500 mW rms, 20 Hz < F < 20 kHz, RL = 8 , G = 0 dB, Cb= 1 F, Cin = 330 nF PSRR Power supply rejection ratio(1) F = 217Hz, RL = 8) Vripple = 200 mVpp, input grounded, Cb=1 F, Cin=330 nF, G=0 dB Common mode rejection ratio(2) F = 217 Hz, RL = 8 , Vincm = 200 mVpp, Cb = 1 F, Cin= 330 nF, G= 0 dB Signal-to-noise ratio (weighted A, G= 0 dB) (RL = 8 , THD + N 0.5%, 20 Hz < F < 20 kHz) Start up gain (when powered up from VCC - see Section 4.9: Volume setting on page 20) Gain range -33
0.5
%
85
dB
CMRR
61
dB
SNR Gs G Gain step size
100 -12 +12 3 -1 10 +1
dB dB dB dB dB ms
Gain Tolerance between theoretical gain set and real gain accuracy twu Wake-up time Cb=1 F Output voltage noise F = 20 Hz to 20 kHz, RL = 8 , G= 0 dB Unweighted A-weighted Differential input impedance Debouncing time
VN Zin tdebounce
21 14 48 60 10 220 3200 75
VRMS k ms ms ms
tautorepeat Time between volume changes trange During autorepeat mode, necessary time to cover the whole gain range
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217 Hz. 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vincm)).
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Electrical characteristics Table 5.
Symbol ICC ISTBY IU/D Voo Po Supply current No input signal, no load Standby current No input signal, VSTBY = GND, RL = 8 Volume control UP/DOWN current 0 VU/D 0.3 VCC Output offset voltage No input signal, RL = 8 , G= 0 dB, floating inputs Output power THD = 1% max, f = 1 kHz, RL = 8 300
TS4974
VCC = +3.3 V, GND = 0 V, Tamb = 25 C (unless otherwise specified)
Parameter Min. Typ. 3.0 260 10 5 380 20 Max. 3.6 2000 Unit mA nA A mV mW
Total harmonic distortion + noise THD + N Po = 500 mW rms, 20 Hz < F < 20 kHz, RL = 8 , G = 0 dB, Cb= 1 F, Cin = 330 nF PSRR Power supply rejection ratio(1) F = 217 Hz, RL = 8 Vripple = 200 mVpp, input grounded, Cb = 1 F, Cin= 330 nF, G = 0 dB Common mode rejection ratio(2) F = 217 Hz, RL = 8 , Vincm = 200 mVpp, Cb = 1 F, Cin = 330 nF, G = 0 dB Signal-to-noise ratio (weighted A, G= 0 dB) (RL = 8 , THD + N 0.5%, 20 Hz < F < 20 kHz) Start up gain (when powered up from VCC - See Section 4.9: Volume setting on page 20) Gain range -33
0.5
%
85
dB
CMRR
61
dB
SNR Gs G Gain step size
100 -12 +12 3 -1 10 +1
dB dB dB dB dB ms
Gain Tolerance between theoretical gain set and real gain accuracy twu Wake-up time Cb= 1 F Output voltage noise F = 20 Hz to 20 kHz, RL = 8 , G = 0 dB Unweighted A-weighted Differential input impedance Debouncing time
VN Zin tdebounce
21 14 48 60 10 220 3200 75
VRMS k ms ms ms
tautorepeat Time between volume changes trange During autorepeat mode, necessary time to cover the whole gain range
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217 Hz. 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vincm)).
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TS4974 Table 6.
Symbol ICC ISTBY IU/D Voo Po Supply current No input signal, no load Standby current No input signal, VSTBY = GND, RL = 8 Volume control UP/DOWN current 0 VU/D 0.3 VCC Output offset voltage No input signal, RL = 8 , G = 0 dB, floating inputs Output power THD = 1% max, f = 1 kHz, RL = 8 Total harmonic distortion + noise Po = 500 mW rms, 20 Hz < F < 20 kHz, RL = 8 , G = 0 dB, Cb= 1 F, Cin= 330 nF Power supply rejection ratio(1) F = 217 Hz, RL = 8 Vripple = 200 mVpp, input grounded, Cb= 1 F, Cin= 330 nF, G= 0 dB Common mode rejection ratio(2) F = 217 Hz, RL = 8 , Vincm = 200 mVpp, Cb = 1 F, Cin= 330 nF, G= 0 dB Signal-to-noise ratio (weighted A, G = 0 dB) (RL = 8 , THD + N 0.5%, 20 Hz < F < 20 kHz) Start up gain (when powered up from VCC - see Section 4.9: Volume setting on page 20) Gain range
Electrical characteristics VCC = +2.6V, GND = 0V, Tamb = 25C (unless otherwise specified)
Parameter Min. Typ. 2.8 230 10 5 200 250 20 Max. 3.4 2000 Unit mA nA A mV mW
THD + N
0.5
%
PSRR
85
dB
CMRR
61
dB
SNR Gs G Gain step size
100 -12 -33 3 -1 10 +1 +12
dB dB dB dB dB ms
Gain Tolerance between theoretical gain set and real gain accuracy twu Wake-up time Cb=1 F Output voltage noise F = 20 Hz to 20 kHz, RL = 8 , G = 0 dB Unweighted A-weighted Differential input impedance Debouncing time
VN Zin tdebounce
21 14 48 60 10 220 3200 75
VRMS k ms ms ms
tautorepeat Time between volume changes trange During autorepeat mode, necessary time to cover the whole gain range
1. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to VCC @ F = 217 Hz. 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vincm)).
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Electrical characteristics Table 7. Output noise
Unweighted filter 20 Hz to 20 kHz Vout (A) G=+12 dB G=+6 dB G=0 dB G=-12 dB G=-33 dB 22 21.5 21 19 17 A-weighted filter Vout (A) 15 14.5 14 13 12
TS4974
8/25
TS4974
Electrical characteristics
Figure 2.
10
THD+N vs. output power
Figure 3.
10
THD+N vs. output power
1
Vcc=2.6V
THD + N (%)
THD + N (%)
RL = 8 G = 0dB F = 1kHz Cb = 1F BW < 125kHz Tamb = 25C
Vcc=5V
Vcc=3.3V
RL = 8 G = 12dB F = 1kHz Cb = 1F BW < 125kHz Tamb = 25C 1
Vcc=5V
Vcc=3.3V Vcc=2.6V
0.1 1E-3
0.01
0.1
Output power (W)
1
0.1 1E-3
0.01
0.1
Output power (W)
1
Figure 4.
10
THD+N vs. output power
Figure 5.
10
THD+N vs. output power
THD + N (%)
1
Vcc=2.6V
THD + N (%)
RL = 16 G = 0dB F = 1kHz Cb = 1F BW < 125kHz Tamb = 25C
Vcc=5V
Vcc=3.3V
RL = 16 G = 12dB F = 1kHz Cb = 1F BW < 125kHz Tamb = 25C 1
Vcc=5V
Vcc=3.3V
Vcc=2.6V
0.1 1E-3
0.01
0.1
1
0.1 1E-3
0.01
0.1
1
Output power (W)
Output power (W)
Figure 6.
10
THD+N vs. output power
Figure 7.
10
THD+N vs. output power
THD + N (%)
THD + N (%)
RL = 8 G = 0dB F = 20kHz Cb = 1F BW < 125kHz Tamb = 25C 1
Vcc=5V
Vcc=3.3V
RL = 8 G = 12dB F = 20kHz Cb = 1F BW < 125kHz Tamb = 25C 1
Vcc=5V Vcc=3.3V
Vcc=2.6V
Vcc=2.6V
0.1 1E-3
0.01
0.1
1
0.1 1E-3
0.01
0.1
Output power (W)
1
Output power (W)
9/25
Electrical characteristics
TS4974
Figure 8.
10
THD+N vs. output power
Figure 9.
10
THD+N vs. output power
THD + N (%)
1
Vcc=2.6V
THD + N (%)
RL = 16 G = 0dB F = 20kHz Cb = 1F BW < 125kHz Tamb = 25C
Vcc=5V Vcc=3.3V
RL = 16 G = 12dB F = 20kHz Cb = 1F BW < 125kHz Tamb = 25C 1
Vcc=5V Vcc=3.3V
Vcc=2.6V
0.1 1E-3
0.01
0.1
1
0.1 1E-3
0.01
0.1
1
Output power (W)
Output power (W)
Figure 10. THD+N vs. frequency
10
Figure 11. THD+N vs. frequency
10 RL = 8 G = 12dB Cb = 1F BW < 125kHz Tamb = 25C
RL = 8 G = 0dB Cb = 1F BW < 125kHz Tamb = 25C Vcc=5V Pout=500mW
THD + N (dB)
THD + N (dB)
1
1
Vcc=5V Pout=500mW
Vcc=3.3V Pout=250mW 0.1
Vcc=2.6V Pout=150mW 0.1
Vcc=3.3V Pout=250mW
Vcc=2.6V Pout=150mW
100
1000
Frequency (dB)
10000
100
1000
Frequency (dB)
10000
Figure 12. THD+N vs. frequency
10
Figure 13. THD+N vs. frequency
10
RL = 16 G = 0dB Cb = 1F BW < 125kHz Tamb = 25C
THD + N (dB)
RL = 16 G = 12dB Cb = 1F BW < 125kHz Tamb = 25C
THD + N (dB)
1 Vcc=2.6V Pout=90mW Vcc=3.3V Pout=150mW Vcc=5V Pout=300mW
1 Vcc=2.6V Pout=90mW Vcc=3.3V Pout=150mW Vcc=5V Pout=300mW
0.1
100
1000
Frequency (dB)
10000
0.1
100
1000
Frequency (dB)
10000
10/25
TS4974
Electrical characteristics
Figure 14. PSRR vs. frequency
0 Vcc = 5V Vripple = 200mVpp G = 0dB Inputs Grounded Tamb = 25C
Figure 15. PSRR vs. frequency
0 Vcc = 5V Vripple = 200mVpp G = 12dB Inputs Grounded Tamb = 25C
-20
-20
-40
PSRR (dB)
-40 Cb=1, 0.47, 0.1F
PSRR (dB)
-60
-60
Cb=1, 0.47, 0.1F
-80
-80
-100 20 100 1000
Frequency (Hz)
-100 10000 20 100 1000
Frequency (Hz)
10000
Figure 16. PSRR vs. frequency
0 Vcc = 3.3V Vripple = 200mVpp G = 0dB Inputs Grounded Tamb = 25C
Figure 17. PSRR vs. frequency
0 Vcc = 3.3V Vripple = 200mVpp G = 12dB Inputs Grounded Tamb = 25C Cb=1, 0.47, 0.1F -60
-20
-20
-40
PSRR (dB)
-40 Cb=1, 0.47, 0.1F
PSRR (dB)
-60
-80
-80
-100 20 100 1000
Frequency (Hz)
-100 10000 20 100 1000
Frequency (Hz)
10000
Figure 18. PSRR vs. frequency
0 Vcc = 2.6V Vripple = 200mVpp G = 0dB Inputs Grounded Tamb = 25C
Figure 19. PSRR vs. frequency
0 Vcc = 2.6V Vripple = 200mVpp G = 12dB Inputs Grounded Tamb = 25C Cb=1, 0.47, 0.1F -60
-20
-20
-40
PSRR (dB)
-40 Cb=1, 0.47, 0.1F
PSRR (dB)
-60
-80
-80
-100 20 100 1000
Frequency (Hz)
-100 10000 20 100 1000
Frequency (Hz)
10000
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Electrical characteristics
TS4974
Figure 20. CMRR vs. frequency
0 Vcc = 5V -10 RL 8 Tamb = 25C -20
CMRR (dB)
Figure 21. CMRR vs. frequency
0 Vcc = 3.3V -10 RL 8 Tamb = 25C -20
CMRR (dB)
-30 -40 -50 -60 -70 -80 100 1000
Frequency (Hz)
-30 -40 -50 -60 -70 G=12dB Cb=1, 0.47, 0.1F G=0dB Cb=1, 0.47, 0.1F
G=12dB Cb=1, 0.47, 0.1F
G=0dB Cb=1, 0.47, 0.1F
10000
-80
100
1000
Frequency (Hz)
10000
Figure 22. CMRR vs. frequency
0 Vcc = 2.6V -10 RL 8 Tamb = 25C -20 -30
CMRR (dB)
Figure 23. SNR vs. supply voltage
110 108 106 104
SNR (dB)
RL=16
102 100 98 96 A - weighted filter F = 1kHz G = 0dB THD + N < 0.5% Tamb = 25C 3.0 3.5 4.0
Vcc (V)
-40 -50 -60 -70 -80
G=12dB Cb=1, 0.47, 0.1F
G=0dB Cb=1, 0.47, 0.1F
RL=8
94 92
100
1000
Frequency (Hz)
10000
90 2.5
4.5
5.0
5.5
Figure 24. SNR vs. supply voltage
110 108 106 104
SNR (dB)
Figure 25. SNR vs. supply voltage
110 108
RL=16
106 104
SNR (dB)
RL=16 RL=8
102 100 98 96 94 92 A - weighted filter F = 1kHz G = +12dB THD + N < 0.5% Tamb = 25C 3.0 3.5 4.0
Vcc (V)
102 100 98 96 94 92 Unweighted filter (20Hz to 20kHz) F = 1kHz G = 0dB THD + N < 0.5% Tamb = 25C 3.0 3.5 4.0
Vcc (V)
RL=8
90 2.5
4.5
5.0
5.5
90 2.5
4.5
5.0
5.5
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TS4974
Electrical characteristics
Figure 26. SNR vs. supply voltage
110
Figure 27. Output power vs. supply voltage
106 104
SNR (dB)
Output power at 1% THD + N (mW)
108
Unweighted filter (20Hz to 20kHz) F = 1kHz G = 12dB THD + N < 0.5% Tamb = 25C
1.0
F = 1kHz BW < 125 kHz Tamb = 25C 8
0.8
102 100 98 96 94 92 90 2.5 3.0 RL=8 RL=16
0.6
16
0.4
32
0.2
3.5
4.0
Vcc (V)
4.5
5.0
5.5
0.0 2.5
3.0
3.5
Vcc (V)
4.0
4.5
5.0
Figure 28. Output power vs. supply voltage
1.4
Output power at 10% THD + N (mW)
Figure 29. Output power vs. load resistance
1.2
1.2 1.0 0.8 0.6
F = 1kHz BW < 125 kHz Tamb = 25C
Output power (W)
1.1 1.0 0.9 8 16 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
Vcc=5.5V Vcc=5V Vcc=4.5V Vcc=4V
THD+N = 1% Cb = 1F BW < 125kHz Tamb = 25C
Vcc=3.3V Vcc=3V
32 0.4 0.2 0.0 2.5
Vcc=2.6V 8 12 16 20 24 28 32
0.0 3.0 3.5
Vcc (V)
4.0
4.5
5.0
Load resistance ( )
Figure 30. Current consumption vs. supply voltage
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3
Vcc (V)
Figure 31. Standby current vs. supply voltage
No load Tamb = 25C
0.4
No load Tamb = 25C
0.3
Istby (A)
Icc (mA)
0.2
0.1
4
5
6
0.0
0
1
2
3
Vcc (V)
4
5
6
13/25
Electrical characteristics
TS4974
Figure 32. Standby voltage vs. supply current Figure 33. Frequency response
4.0 No load 3.5 Tamb = 25C 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5
Vstby (V)
Vcc=5V
Gain (dB)
Icc (mA)
Vcc=2.6V
Vcc=3.3V
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4
Cin=4.7F Vcc = 5V, 3.3V, 2.6V ZL = 8 + 500pF Tamb = 25C
Cin=330nF Cin=4.7F
G=+12dB
Cin=330nF Cin=4.7F
G=+6dB
Cin=330nF 20 100 1000
Frequency (Hz)
G=0dB 10000 20k
2.0
2.5
Figure 34. Frequency response
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4
Figure 35. Power dissipation vs. output power
0.8 Vcc = 5V 0.7 F = 1kHz THD+N < 1%
Power Dissipation (W)
Cin=4.7F
Cin=330nF Cin=4.7F
G=+12dB
Vcc = 5V, 3.3V, 2.6V ZL = 16 + 500pF Tamb = 25C
0.6 0.5 0.4 0.3 0.2 0.1 RL=32 RL=16 RL=8
Gain (dB)
Cin=330nF Cin=4.7F
G=+6dB
Cin=330nF 20 100 1000
Frequency (Hz)
G=0dB 10000 20k
0.0 0.0
0.2
0.4
0.6
0.8
1.0
Output Power (W)
Figure 36. Power dissipation vs. output power Figure 37. Power dissipation vs. output power
Vcc = 3.3V F = 1kHz 0.3 THD+N < 1%
Power Dissipation (W)
Power Dissipation (W)
0.20
Vcc = 2.6V 0.18 F = 1kHz THD+N < 1% 0.16 RL=8 0.14 0.12 0.10 0.08 0.06 0.04 0.02 RL=32 RL=16 RL=8
0.2 RL=16
0.1
RL=32
0.0 0.0
0.1
0.2
0.3
0.4
0.00 0.00
0.05
0.10
0.15
0.20
0.25
Output Power (W)
Output Power (W)
14/25
TS4974
Electrical characteristics
Figure 38. Power derating curves
DFN10 Package Power Dissipation (W)
1.5 with 4 layers PCB 1.0
0.5 AMR Value
0.0
0
25
50
75
100
125
Ambiant Temperature ( C)
15/25
Application information
TS4974
4
4.1
Application information
Differential configuration principle
The TS4974 is a monolithic full-differential input/ output power amplifier with a digital volume control. It has an internal gain range of -33 dB up to +12 dB, by steps of 3dB (see Section 4.9: Volume setting on page 20), which offers better performance in terms of noise immunity and PSRR. The advantages of a full-differential amplifier are:

Very high PSRR (power supply rejection ratio). High common mode noise rejection. Virtually zero pop without additional circuitry, giving a faster start-up time compared to conventional single-ended input amplifiers. Easier interfacing with differential output audio DAC.
In theory, the filtering of the internal bias by an external bypass capacitor is not necessary. But, to reach maximum performance in all tolerance situations, it is better to keep this option.
4.2
Low frequency response
The input coupling capacitors block the DC part of the input signal at the amplifier inputs. Input capacitors Cin and input impedance Zin forms a first-order, high pass filter with -3 dB cut-off frequency.
FCL = 1 2 x x Rin x Cin (Hz)
Note:
Differential input impedance of 60 k is a typical value, and there is tolerance around this value. From Figure 39 you can easily establish the Cin value required for a cut-off frequency of -3 dB. Figure 39. -3dB lower cut-off frequency vs. input capacitance
100 All gain setting Tamb=25C
Low -3dB Cut Off Frequency (Hz)
Minimum Input Impedance
Typical Input Impedance 10 Maximum Input Impedance 0.1 0.5
Input Capacitor Cin (F)
1
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TS4974
Application information
4.3
Power dissipation and efficiency
Assumptions:

Load voltage and current are sinusoidal (Vout and Iout) Supply voltage is a pure DC source (VCC)
The output voltage is:
V out = V peak sint (V)
and
V out I out = ------------ (A) RL
and
V peak 2 P out = -------------------- (W) 2R L
Therefore, the average current delivered by the supply voltage is: Equation 1
V peak I CC AVG = 2 ---------------- (A) R L
The power delivered by the supply voltage is: Psupply = VCC ICC AVG (W) Therefore, the power dissipated by each amplifier is: Pdiss = Psupply - Pout (W) Equation 2
2 2V CC P diss = ---------------------- P out - P out RL
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Application information and the maximum value is obtained when:
Pdiss -------------------- = 0 P out
TS4974
and its value is: Equation 3
Pdiss max = 2 Vcc 2 2RL (W)
Note:
This maximum value is only dependent on the power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply: Equation 4
P out V peak = ------------------ = -------------------P supply 4V CC
The maximum theoretical value is reached when Vpeak = VCC, so:
= ---- = 78.5% 4
The maximum die temperature allowable for the TS4974 is 125C. However, in case of overheating, a thermal shutdown set to 150 C, puts the TS4974 in standby until the temperature of the die is reduced by about 5 C. To calculate the maximum ambient temperature Tamb allowable, you need to know:

Power supply voltage value, VCC Load resistor value, RL The package type, RTHJA
Example: VCC=5 V, RL=8 , RTHJAflip-chip=80 C/W (125 mm2 copper heatsink). Using the power dissipation formula given above in Equation 3 this gives a result of: Pdissmax = 633mW Tamb is calculated as follows: Equation 5
T amb = 125 C - R TJHA x P dissmax
Therefore, the maximum allowable value for Tamb is: Tamb = 125-80x0.633 = 74.3C
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TS4974
Application information
4.4
Decoupling of the circuit
Two capacitors are needed to correctly bypass the TS4974. A power supply bypass capacitor CS and a bias voltage bypass capacitor Cb. CS has particular influence on the THD+N in the high frequency region (above 7 kHz) and an indirect influence on power supply disturbances. With a value for CS of 1 F, you can expect similar THD+N performance to that shown in the datasheet. In the high frequency region, if CS is lower than 1 F, it increases the THD+N, and disturbances on the power supply rail are less filtered. On the other hand, if CS is higher than 1 F, the disturbances on the power supply rail are more filtered. Cb has an influence on THD+N at lower frequencies, but its function is critical to the final result of PSRR (with input grounded and in the lower frequency region).
4.5
Wake-up time (tWU)
When the standby is released to put the device ON, the bypass capacitor Cb is not charged immediately. As Cb is directly linked to the bias of the amplifier, the bias will not work properly until the Cb voltage is correct. The time to reach this voltage is called the wake-up time or tWU and is specified in the tables in Section 3: Electrical characteristics on page 5, with Cb=1 F. During the wake-up phase, the TS4974 gain is close to zero. After the wakeup time, the gain is released and set to its nominal value. If Cb has a value other than 1 F, refer to Figure 40 to establish the wake-up time. Figure 40. Startup time vs. bypass capacitor
15 Tamb=25C Vcc=5V
Startup Time (ms)
10 Vcc=2.6V Vcc=3.3V 5
0 0,4 0,8 1,2 1,6 Bypass Capacitor Cb (F) 2,0
4.6
Shutdown time
When the standby command is set, the time required to put the two output stages in high impedance and the internal circuitry in shutdown mode is a few microseconds.
Note:
In shutdown mode, the Bypass pin and Vin+, Vin- pins are short-circuited to ground by internal switches. This allows a quick discharge of Cb and Cin capacitors.
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Application information
TS4974
4.7
Pop performance
Due to its fully differential structure, the pop performance of the TS4974 is close to perfect. However, due to mismatching between internal resistors Rin, Rfeed, and external input capacitors Cin, some noise might remain at startup. To eliminate the effect of mismatched components, the TS4974 includes pop reduction circuitry. With this circuitry, the TS4974 is close to zero pop for all possible common applications. In addition, when the TS4974 is in standby mode, due to the high impedance output stage in this configuration, no pop is heard.
4.8
Single-ended input configuration
It is possible to use the TS4974 in a single-ended input configuration. The schematic in Figure 41 shows an example of this configuration. Figure 41. Typical single-ended input application
VCC
Rpu1 Volume DOWN S1 470k
VCC
Rpu2 470k
VCC
Volume UP
S2 Cs Rpd1 470k Rpd1 470k 1F
U1
UP
DIGITAL VOLUME CONTROL
Vin P1 Cin1
DOWN
Vcc
10
7
6
1
330nF Cin2
Vin-
Vout-
9
Speaker
2
330nF
Vin+
+
BIAS STBY
STBY GND
Vout+
8
8 Ohms
3
Cb 1F
BYP ASS
TS4974 DFN10
4
STBY control
4.9
Volume setting
The TS4974 features a digital volume control with an internal gain range of -33 dB up to +12 dB, by steps of 3 dB. When the device is powered up from VCC (and not from the standby pin), an initial gain of -12dB is internally fixed. When standby mode is activated, the gain value is memorized and held until standby is released.
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5
TS4974
Application information The volume is controlled by means of two pins, UP/DVC and DOWN/DVC. When the VIL voltage is applied, it activates the increase or decrease in gain. When one of the input pins is grounded, volume changing is activated. When both volume UP and DOWN functions are activated at the same time, there is no effect on the volume. The UP/DVC and DOWN/DVC inputs need to be pulled-up or pulled-down, so a pair of external pull-up or pull-down resistors are required. When pull-up resistors are used, it is dependent on the application which values of resistors you should choose in the range from 10k to 1M. The current flowing through the switch S1 or S2 during volume changing is adjusted by the value of the pull-up resistors. When pull-down resistors are used, the values are chosen in the range from at least 430k to 1M (a value 470k is recommended). Typically, in this case a 10A current flows through the switch S1 or S2 during volume changing. Table 2 on page 3 indicates the values of the VU/D voltages required to activate an increase or decrease in volume. The volume can also be controlled by a microcontroller. In this case, transistors can be used as switches for grounding the UP/DVC and DOWN/DVC pins. The TS4974 integrates a debouncing system which does not take into account UP or DOWN pulses that are shorter than the tdebounce time. In addition, an autorepeat function is implemented. When a continuous voltage is applied to the UP or DOWN pin, the gain is continuously increased or decreased after a certain time called tautorepeat. The first period of each autorepeat sequence is longer (tautorepeat x 1.5) to avoid any parasitic activation. In this mode, the time trange is necessary to cover the whole gain range of the device. Figure 42 explains the meaning of the debounce, autorepeat and range times (respectively tdebounce, tautorepeat and trange). It shows how the volume increases over the whole volume range from the minimum gain -33 dB to the maximum gain +12 dB by 3 dB steps. Figure 42. Example of volume change
Gain (dB) 1.5 x tautorepeat tautorepeat
G=+12dB
G=3dB
G=-33dB
Time VUP
tdebounce trange
Time
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Application information
TS4974
4.10
Notes on PSRR measurement
What is the PSRR?
The PSRR is the power supply rejection ratio. The PSRR of a device is the ratio between a power supply disturbance and the result on the output. In other words, the PSRR is the ability of a device to minimize the impact of power supply disturbance to the output.
How is the PSRR measured?
The PSRR is measured as shown in Figure 43. Figure 43. PSRR measurement
VCC
Rpu1 Volume DOWN S1 470k
VCC
Rpu2 470k
Vripple
Volume UP S2 Vcc Rpd1 470k Rpd1 470k
U1
UP
DIGITAL VOLUME CONTROL
Cin1
1
10 Ohms 330nF Cin2
DOWN
Vcc
10
7
6
Vin-
Vout-
9
RL 8 Ohms
2
330nF 10 Ohms Cb 1F
Vin+
+
BIAS STBY
STBY GND
Vout+
8
3
BYP ASS
TS4974 DFN10
4
STBY control
Principles of operation

The DC voltage supply (VCC) is fixed The AC sinusoidal ripple voltage (Vripple) is fixed No bypasss capacitor Cs is used
The PSRR value for each frequency is calculated as:
RMS ( Output ) PSRR = 20 x Log --------------------------------- ( dB ) RMS ( Vripple )
RMS is an rms selective measurement.
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5
TS4974
Package information
5
Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com. Table 8. DFN10 3x3 exposed pad package mechanical data
Dimensions Ref. Min. A A1 A2 A3 b D D2 E E2 e L 0.3 1.49 2.21 0.18 0.80 Millimeters Typ. 0.90 0.02 0.70 0.20 0.23 3.00 2.26 3.00 1.64 0.50 0.4 0.5 11.8 1.74 58.7 2.31 87.0 0.30 7.1 Max. 1.00 0.05 Min. 31.5 Mils Typ. 35.4 0.8 25.6 7.9 9.1 118.1 89.0 118.1 64.6 19.7 15.7 19.7 68.5 91.0 11.8 Max. 39.4 2.0
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Ordering information
TS4974
6
Ordering information
Table 9. Order codes
Temperature range -40 C to +85 C Package DFN10 Packing Tape & reel Marking A74
Part number TS4974IQT
7
Revision history
Date 1-Nov-2005 1-Oct-2006 25-Oct-2006 Revision 1 2 3 Changes Mechanical data updated for DFN10 package. Preliminary data. Final datasheet. Updated Figure 1, Figure 41, and Figure 43. Added Table 3. Modified Section 4.9 on page 20 to add information on pull-up and pull-down resistors.
10-May-2007
4
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TS4974
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